Pipeline: overlapping the handling of instructions
Just as you overlap washing, drying and folding laundry, a CPU overlaps the stages of instruction handling. This is also where slow branches come from.
If one instruction is handled to the end before the next begins, most of each stage's circuitry sits idle. A pipeline handles a different instruction in each stage at the same time.
| Clock | 1 | 2 | 3 | 4 |
|---|---|---|---|---|
| Fetch | A | B | C | D |
| Decode | A | B | C | |
| Execute | A | B |
The time for one instruction is the same, but one finishes every clock, so throughput rises. The Cortex-M3/M4 has a 3-stage pipeline and the M7 a 6-stage one.
Why branches are expensive
Whether a conditional branch is taken is only decided at the Execute stage. The instructions that entered the pipeline before then have to be thrown away, and refilling from the new address costs a few clocks. So in a short loop that runs often, simply reducing branches makes it faster.
Where you see it in practice
- The "interrupt latency of 12 clocks" in a datasheet includes the time to empty and refill the pipeline.
- If Flash is slower than the CPU, wait states occur and the pipeline stalls. The Flash prefetch and ART accelerator on STM32 are there to reduce this.