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Notes / Digital Logic

Logic levels and interfacing: connecting 3.3 V and 5 V

From what voltage a signal reads as 1, how push-pull and open-drain differ, and how to connect chips with different voltages.

GROUND EMBEDDED · NOTEDigital Logic 07Logic levels and interfacesANDABY

Logic levels

Read as LOW0 ~ 0.8 VNot guaranteed0.8 ~ 2.0 VRead as HIGH2.0 ~ 3.3 V
How 3.3 V logic reads its input. In the middle band neither 0 nor 1 is guaranteed.

A chip reads an input above a certain voltage as 1 and below a certain voltage as 0. The region in between is undefined.

Value Meaning 3.3 V CMOS example
VIH Minimum input read as 1 About 2.0 V
VIL Maximum input read as 0 About 0.8 V
VOH Minimum output when driving 1 About 2.4 V or more

Feeding a 3.3 V MCU output (about 3.3 V) to a 5 V TTL input (VIH 2.0 V) is usually fine, but it may fall short for a 5 V CMOS input (VIH 3.5 V). In the other direction, a 5 V output into a 3.3 V input can destroy the chip, so check in the datasheet whether the pin is 5 V tolerant (FT).

Push-pull and open-drain

  • Push-pull: actively pulls to the supply for 1 and to ground for 0. Fast, and the normal choice.
  • Open-drain: pulls to ground only for 0 and lets go for 1. An external pull-up resistor makes the 1. Several chips can share one line, which is why I2C works this way.

Level shifting

5 V sensor outputLevel shiftdivider · shifter IC3.3 V MCU input
Put level shifting between two chips with different voltages.

One-way signals are converted with a resistor divider or a dedicated buffer chip; bidirectional open-drain signals such as I2C use a level shifter made of one MOSFET and two pull-ups.

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