ARM Cortex-M overview: from M0 to M7
How the Cortex-M cores differ, and how companies such as ST and NXP build MCU families by adding peripherals to cores designed by ARM.
ARM sells CPU core designs, and semiconductor companies such as ST, NXP and Infineon add Flash, SRAM and peripherals to those cores to make MCUs. So an STM32 and an NXP chip share the core instructions but have completely different GPIO and timer registers.
| Core | Characteristics | Typical MCUs |
|---|---|---|
| M0 / M0+ | Smallest and lowest power, few instructions | STM32G0, RP2040 |
| M3 | Hardware divide, balanced | STM32F1 |
| M4 | DSP instructions + single-precision FPU | STM32F4, STM32G4 |
| M7 | 6-stage pipeline, cache, double-precision FPU | STM32F7, H7 |
| M33 | M4 class + security (TrustZone) | STM32L5, U5 |
What every core provides
- NVIC: the interrupt controller
- SysTick: a 24-bit timer used for the RTOS tick
- Debug interface: SWD
- CMSIS: standard headers for the core registers
How to choose
With a lot of floating-point calculation, as in motor control, an M4 or above with an FPU; for a battery sensor node, an M0+; for graphics and heavy computation, an M7. More important than the core is whether the chip has the peripherals you need (advanced timers, number of ADCs, CAN FD).