SPI
One bit per clock, with master and slave exchanging data at the same instant. Chip select, the four modes, and how a mode mismatch shifts the value you read.
Loading the 3D scene
Send
Enter two digits using 0-9 and A-F.
Bus waveform CS · SCK · MOSI · MISO
Dashed vertical lines mark when the master samples. The yellow band is the current position.
Results
- Value sent (MOSI)
- Value the slave sent
- Value the master read (MISO)
- Time per byte
The mode does not match the slave, so the value was read shifted by one bit. The transfer looks fine, but the value is wrong.
Try this
- Press Send. First the CS line goes LOW. Only that slave wakes up; the other slave leaves MISO floating (grey).
- On every clock one bit leaves on MOSI and, at the same moment, one bit arrives on MISO. Watch TX and RX fill together on the master's screen.
- Change the target to Slave B: CS1 goes LOW and B answers. Clock and data lines are shared, but each chip has its own CS.
- Switch the mode from 0 to 3. The clock now idles HIGH, yet the value reads the same, because both modes sample on the rising edge.
- Choose mode 1 or 2 and the master samples on the falling edge, so the received value is shifted by one bit. A mode error does not stop communication; it makes the value wrong.
How to read it
SPI is two shift registers, one in the master and one in the slave, joined in a ring. Eight clocks from the master swap the two bytes completely. That is why the master must send something even when it only wants to read, and why something always comes back when it writes.
| Mode | Clock idle (CPOL) | Sampling edge (CPHA) |
|---|---|---|
| 0 | LOW | first = rising |
| 1 | LOW | second = falling |
| 2 | HIGH | first = falling |
| 3 | HIGH | second = rising |
Both slaves in this lab are assumed to sample on the rising edge and change their output on the falling edge. Many sensors and flash memories work this way, which is why their datasheets list both mode 0 and mode 3.
This lab is also available in Korean. More labs: all 3D labs.